Monthly Bulletin

Cadence RF SiP Methodology Kit

CMC is pleased to introduce the Cadence RF System-in-Package (SiP) Methodology Kit to Canadian university clients. The RF SiP Methodology Kit includes reference designs, tutorials, and guidelines for best practices needed to implement advanced system-in-package mixed-signal design.

This kit guides new users through complete how-to tutorials and is intended to train researchers and students to implement circuits and systems that involve multi-die integration, 3D die-stacking, and die/package/substrate co-design.

Kit features and benefits:

• Comprehensive step-by-step training manuals to guide users through a complete design flow
• Library of reference designs, components, models, and simulation/verification plans
• Integrated flow from Cadence Virtuoso to package-level SiP design
• Unified schematic and simulation environment for RF/analog design
• Design, modeling, and synthesis of passive components in package
• Interactive editing of die-to-die and substrate interconnects
• System-level functional, performance, and closed-loop verification
• Package place-and-route, optimization, validation, and tapeout

Product access and licensing information:

To request access to this product or to learn more, please visit:

https://www1.cmc.ca/clients/design/cadence_rf_sip_kit.php

Related Product/Training: 

Training courses on RF SiP methodology are being planned for delivery in the April-August timeframe. Stay tuned for further information.

Future Support: As of April 2010 the following value-add services will also be available to CMC Subscription holders:

• Access to the kit (if not already acquired) delivered in a Canada-wide supported configuration
• Kit updates
• CMC engineering support
• Application notes related to the technology
• 85% discount on the 3-day SiP training course ($400 rather than $2500 per seat) - limited availability
• Eligibility for up to $750 in financial assistance towards travel and living expenses to attend the RF SiP methodology training

  IN THIS ISSUE 

Competitions

Application Notes

News/Events

Get a CMC Account

Competitions

 Open Competitions

• Agilent ADS (Teaching and Research Licenses)
• AP1000 Development Boards
• Nanofabrication
• Carrier Platform for Microfluidics Research
• Flip chip attachment
• Encapsulation
• Hermetic sealing and selective encapsulation
• Vacuum packaging
• Compact Wireless Microsystem

For more information on our open competitions or to apply, please visit our Competition Homepage.

 Fabrication Deadlines

Request for Manufacturing Resources (RFMR) Deadlines:

• 1001CS 65-nanometre CMOS (TSMC); March 10, 2010
• 1001CD .35-micron CMOS; March 10, 2010
• 1003PE EPI-Only InP/GaAs Based Technology; March 31, 2010

Design Submission Deadlines:

• 1001MM MetalMUMPs; March 10, 2010
• 1001FS Sensonit; March 17, 2010
• 1002MU PolyMUMPs; March 31, 2010

Fabrication procedures and forms.

News and Events 

News

• Government of Canada invests in Microelectronics Research; February 9, 2010 More...
  

Events

• Agilent EEsof Overview Webinar now available online More...
• Designing for Photonics Fabrication; Vancouver, BC March 8, 2010 Contact us
  
• Designing for Photonics Fabrication; Edmonton, AB March 9, 2010 Contact us
  
• CMOS Emerging Technologies; May 19-21, 2010 More...

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Featured Application Notes

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  Prepared by Jean-Samuel Chenard, MEng, under the Supervision of Prof. Zeljko Zilic., Integrated Microsystems Laboratory, McGill University.

• Developing Applications for XD2000i System Using Mitrion-C

Prepared by Alexandru Ciobanu, M.Eng student, McGill University, under the supervision of Prof. Warren J. Gross.

• Characterization of a Quantum-Dash Fabry-Perot Laser for Clock Recovery Applications

Prepared by Xuefeng Tang and John Cartledge, Department of Electrical and Computer Engineering, Queen's University.

65-nanometre Update

CMC is pleased to introduce subsidized fabrication access to the TSMC65nm (CRN65LP) technology, for Canadian university researchers. The supported 65nm technology is a mixed-signal/RF 1P9M low-power process with 1.2/2.5V devices and ultra-thick (34kA) top metal. The design kit for this process includes RF libraries and models.

The first TSMC 65nm fab run is scheduled for May 26, 2010. The deadline for area requests is March 10, 2010.

CMC Subscriptions connect you with information, tools, services and price discounts not otherwise available - adding value to microsystems R&D. More...